The increasing demand for digital Integrated Circuits (IC) comes with a diversification of the target applications. IC designers are facing new challenges to meet the various design constraints imposed by the customers, from high-end ultrafast designs to low-frequency low-cost ultra-low-power applications. At the same time, the scaling trend of MOSFET leads to the development of nanoscale CMOS processes driven by Moore's law. This development comes at the expense of high leakage currents. When working on low-frequency ultra-low-power applications, the overall power consumption is no longer dominated by dynamic power but by static power due to leakage currents, especially with deep submicron technologies.
The design scope of CMOS digital IC's can be divided into three categories. In the first category stand the high-end applications that have to support GHz-range operating frequencies to build competitive computers, super-calculators, etc. The important figure of merit of performance for digital IC's from this category is the energy-delay product. Static and dynamic CMOS circuits have proven their efficiency for these applications.
In the second category of CMOS digital IC's stand the portable applications like cell phones and PDA's that need to operate with minimum energy per operation. Minimization of the energy per operation can be achieved by lowering the power supply. Therefore, static sub-threshold CMOS circuits are very effective for these applications, as described by R. Gonzalez, B. Gordon and M. Horowitz in “Supply and Threshold Voltage Scaling for Low Power CMOS”, IEEE Journal of Solid-State Circuits, Vol. 32 (8), 1997, pp. 1210-1216.
The third category contains the ultra-low-power applications. Such circuits either have to operate during a long period with reduced battery capacity or are scavenging energy from the environment. Design has to be low cost avoiding off-chip components like extra bias voltage supplies. Typical application domains are wristwatches, bio-medical implanted devices, sensor networks, RFID's (radio frequency identification). These circuits often have to perform its task in a slow repetitive fashion. Therefore, the figure of merit for performance considered here is no longer the energy per operation but the total energy consumed during one task repetition period. This energy comes from the dynamic and static power consumption as:
                              E          T                =                                            N              SW                        ⁢                                                            C                  TOT                                ⁢                                  V                  DD                  2                                            2                                +                                    V              DD                        ×                          I              STAT                        ×                          T              PER                                                          (        1        )            where NSW is the number of node switchings to perform one occurrence of the task. CTOT is the total switched capacitance of the circuit, VDD the power supply, ISTAT the total static current of the circuit and Tper is the task repetition period. The timing constraint is given by the task execution time that has to be smaller than Tper. If Tper is long for the ultra-low-power applications, the main part of the consumed energy comes from the static power dissipation. Reduction of the static power can be achieved again by lowering VDD. However, there is a lower bound for VDD because of the degradation of the CMOS gate output swing, as described by B. H. Calhoun, A. Wang and A. Chandrakasan in “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE J. of Solid-State Circuits, Vol. 40 (9), 2005, pp. 1778-1786. The static power consumption cannot be reduced by orders of magnitude by lowering VDD. Efforts are thus devoted to the minimization of the static current. Static current of digital CMOS gates is given by the OFF-current IOFF of the devices at gate-to-source voltage VGS=0V. IOFF is due to the leakage currents: gate, junction leakage and sub-threshold channel leakage currents. In deep-submicron technologies, sub-threshold current is the dominating leakage source, as acknowledged in F. Fallah and M. Pedram in “Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits”, IEICE Trans. on Electronics, Vol. E88-C (4), 2005, pp. 509-519. In this patent, focus is placed on the reduction of the sub-threshold current. The goal is to lower this leakage source to the current level of the other leakage sources in order to minimize the total static current of digital gates.
Sub-threshold leakage current depends exponentially on the device threshold voltage VT. It increases dramatically as VT is lowered to keep high-driving capability of high-speed technologies when scaling VDD. The traditional way of limiting sub-threshold leakage is to use high-VT devices to implement the digital gates. This is a very efficient technique but it requires the use of a high-VT process. Another technique to reduce the sub-threshold leakage is the application of a reverse body bias. However, it has been shown by A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar and V. De in “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs”, Proc. of the IEEE/ACM International Symposium on Low-Power Electronics and Design, 2001, pp. 207-212, that reverse body bias has limited effectiveness at shorter channel lengths and low VT. It also increases junction leakage and two extra bias voltage supplies are needed too, which is a problem regarding low-cost integration.
Other static current reduction techniques are based on sleep-mode features. After having achieved the task in active mode, the circuit goes into sleep-mode for the remaining part of Tper. In sleep mode, sub-threshold leakage current and thus static current is lowered by gating the power supply with high-VTcut-off devices, as described by S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada in “1-V Power Supply High-Speed Digital Circuits Technology with Multi-threshold-Voltage CMOS”, IEEE J. of Solid-State Circuits, Vol. 30 (8), 1995, pp. 847-854. A dual-VT process is required. Power gating can be achieved with single-VT process by overdriving the gate of the cut-off devices with negative VGS. This is described by H. Kawaguchi, K. Nose and T. Sakurai in “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current”, IEEE J. of Solid-State Circuits, Vol. 35 (10), 2000, pp. 1498-1501. As with the reverse-body-bias technique, the drawback is the need for extra bias voltage supplies.